Recently, the power-supply voltage for many commercial very large scale integration (VLSI) chips has decreased to 3 V, and it will continue to decrease to even lower levels. This trend is driven by three factors simultaneously: feature-size scaledown in VLSI technologies, power management in large VLSI chips, and increased demand for mobile or portable battery-operated products. This low-power trend presents great challenges to analog and mixed analog-digital chip designers, particularly since integrated circuits are generally designed in VLSI technologies that are developed primarily to meet the needs of digital applications, such as computation and storage.